In reply to ben@SystemVerilog.us:
Hi Ben, thanks for your reply. It is very helpful.
I have two doubts about the code.
repeat(10) begin : rpt10
// 1.After REQ assert, ACK has to be asserted in 1~10 clk cycle
//[ML]---------------------------------------------------------------
//[ML]should it be $rose(ack) instead of ack?
//[ML]if($rose(ack)) begin : got
//[ML]---------------------------------------------------------------
if(ack) begin : got
gotack=1'b1;
disable rpt10;
end : got
@(posedge clk);
end : rpt10
a_gotack: assert(gotack) else `uvm_error("MYERR", "No ack after req in 10")
if(!gotack) disable req2end;
begin : Reqfor7
// 2.REQ should stay high for 5~7 clk cycles before goes low
-> e3;
//[ML]------------------------------------------------------
//[ML] how to check lower bound >=5 clk cycles??
//[ML]------------------------------------------------------
repeat(7) begin : rpt7
if(!req) begin : afell_req
reqhi=1'b1;
disable afell_req;
end : afell_req
@(posedge clk);
end : rpt7
areqhi7 : assert(reqhi) else `uvm_error("MYERR", "No reqhi for 7")
if(!reqhi) disable Reqfor7; // may not be needed
end : Reqfor7