SystemVerilog checker function/task for two input arbiter

SystemVerilog
, ,
4

Without assertion , this can be achieved through the following snippet of code .
Logic is not fully tested


int unsigned req_cnt =0;
int unsigned gnt_cnt =0;
int unsigned req_clk_cnt =0 ;
int unsigned gnt_clk_cnt =0;
      forever begin 
           @(posedge clk)
           if(req) begin
                  req_cnt++;
                   req_clk_cnt=0;
             end 
           else req_clk_cnt++;
           if (gnt) begin 
                if(req_cnt !=0) req_cnt--;
                if(req_cnt ==0) $error ("Gnt is asserted without Req");
                if((req_clk_cnt < gnt_clk_cnt) && (gnt_clk_cnt >4)) gnt_clk_cnt -=req_clk_cnt;
              end 
            else begin 
                  if(req_cnt !=0) gnt_clk_cnt++;
              end 
         if (gnt_clk_cnt >4) $error ("gnt is not asserted within [1:4] cycles");  
      end