Systemverilog assertions

In reply to vinayks:
How is (a==5’d1||a==5’b0) anywhere close to meaning “a is equal to any value from 0 to 31”
Based on your example, I think you meant to say:

“When a is equal to any value from 0 to 31 ,then in the next 4 cycles ,either b or c should be equal to what a was in the first cycle, and a cannot be the same as it was in the first cycle.”

property p;
   int v;
   @(posedge CLK) (a inside {0:31]}, v = a) |=> (v inside {b,c} && a != v)[*4];
endproperty