SystemVerilog Assertions Free/Symbolic Variable Usage Error

SystemVerilog
, , ,
2

You can only access for-generate instances with constants. You can do that with another for-generate loop.

property sram(index);
  @(posedge clk) disable iff(!resetn)
  bank_sel == index && 
  sram_top.u_0.sram_col_inst[index].sram_row.cen[sram_sel]
  |->
   …
endproperty

for(genvar i=0;i<MAX_SEL;i++) begin : bank
   assert property(sram(i));
end
1 Like