Systemverilog assertion - How do I check the stable signal after implication operator?

SystemVerilog
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7

In reply to UVM_LOVE:


idle[*0:$](repetition with unbounded range) is equivalent to 
  !idle or idel ##1 idel or idel ##1 idel ##1 idel or .. so on. 
##[0:$] idel (its unbounded range) is equivalent to 
  idel or !idel ##1 idel or !idel ##1 !idel ##1 idel or .. so on.