System verilog

In reply to srikanth.verification:

sorry calling in intial block num_2.num_5 but getting this error. ERROR VCP2020 “begin…end pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 tokens are missing.” “testbench.sv” 28 11
ERROR VCP2000 “Syntax error. Unexpected token: endclass[_ENDCLASS]. This is a SystemVerilog keyword since IEEE Std 1800-2005 and cannot be used as an identifier. Use -v2k5, -v2k or -v95 argument for compilation.” “testbench.sv” 28 11
ERROR VCP2020 “module/macromodule…endmodule pair(s) mismatch detected. 1 <module/macromodule> tokens are missing.” “testbench.sv” 46 29
ERROR VCP2000 “Syntax error. Unexpected token: endmodule[_ENDMODULE].” “testbench.sv” 46 29
FAILURE “Compile failure 5 Errors 0 Warnings Analysis time: 0[s].”