System verilog FIFO

SystemVerilog
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3

In reply to sbellock:

During a write to FIFO, push the data into the queue and during a read from FIFO pop the data from the queue and compare the dataout of FIFO with the data popped from the queue. Remember that push & pop should be in opposite direction. While pushing & popping the data from the queue you can compare the size of the queue to set empty & full flags.A small snippet of code is shown below for your reference(Considering FIFO of 8 bits wide & 16 bytes depth)



bit[7:0]fifo_model[$];
bit [7:0]ref_data;
bit full;
bit empty;
if(xtn.rst)
  begin
   fifo_model.delete();
   full = 0;
   empty = 1;
  end

if(xtn.wr)
  begin
    if(fifo_model.size==16)
      full = 1; 
    else
     fifo_model.push_back(xtn.data_in);
  end

if(xtn.rd)
  begin
    if(fifo_model.size == 0)
       empty =1;
    else
      begin
        ref_data = fifo_model.pop_front();
        if(xtn.data_out == ref_data)
          $display("DATA COMPARED SUCESSFULLY");
       else
          $display("DATA COMPARISION FAILED");
     end
   end

You can add the logic to compare the full & empty conditions as well

Regards,
Shanthi V A