System Verilog Covergroups

Coverage
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4

In reply to dave_59:

Hi Dave ,

I was trying the following code ::


 bit [3:0]  adr1 ;

   covergroup adr1_cg ;  
   
      ac : coverpoint adr1    
      {   
        illegal_bins  illvalues  =  { [12:15] }  ;   
      }   
    
   endgroup                      
 
   adr1_gc  cg1  =  new() ;

   initial  begin

     #2 ; adr1 = 10 ;  cg1.sample() ;
    
     #2 ; adr1 = 8  ;  cg1.sample() ;

     #2 ; adr1 = 14 ;  cg1.sample() ;
        
     #2 ; adr1 = 4  ;  cg1.sample() ;
    
   end

In any case hitting an illegal bin should throw out all of the coverage collected for that test.

I checked that the LRM doesn’t mention anything regarding this .

On trying the above code I see that tools have different behavior ,
some consider auto[4] covered ( Value after illegal_bin hit ) whereas some don’t

So I assume this would also fall under Tool Specific behavior ( which I understand isn’t discussed on this forum )