System Verilog , Coverage

Coverage
,
1

For the following snippet of code predict the coverage % and also write the covered
and uncovered bins.


module cg_test();
  bit [4:0]a;
  covergroup cg;
    c1:coverpoint a {
       option.at_least = 2;
       bins a1[10]={[0:$]};
    }
  endgroup

  cg c1;

  initial begin
    c1 = new();
    for(int i = 0;i < 16;i++) begin
      a = i;
      c1.sample();
    end
    a = 4'b1010;
    c1.sample();
  end
endmodule
2

In reply to AKARSHIT:

There’s no need to predict anything here. Why can’t you run the example and get a report on the coverage?