System verilog constraint

SystemVerilog
1

I am trying to randomize a n*n array and make it unique without foreach or unique keyword. why doesn’t the below code produce unique values?

class tb;
  rand bit [3:0] arr[2][2];
  constraint ab_c {
    arr.sum(item1) with (item1.sum(item2) with (int'(item2))) == 1; }
endclass

module t;
  tb t1;
  initial begin
    t1 = new();
    repeat (5) begin
    if (!t1.randomize()) $display("Error");
      $display("%p",t1.arr);
    end
  end
  
  
endmodule
2

The constraint you wrote says the sum of all the elements must equal to 1.

Doing this with reduction methods only requires four levels of reduction.
This works, but I’m not going to explain it.

constraint ab_c {
    arr.and(item1) with (item1.and(item2) with (
      arr.and(item3) with (item3.and(item4) with ( 
        (item1.index == item3.index && item2.index == item4.index) ||
        item2 != item4 ))));
  }
3

I believe your intention was to write it as ::

class tb;
  rand bit [2:0] arr[2][2];
  
  constraint ab_c {            
                      foreach(arr[i,j])
    arr.sum(item1) with (item1.sum(item2) with ( int'( item2 == arr[i][j] ) )) == 1; 
                   }
endclass
4

@Have_A_Doubt, their intent was to write it without using a foreach expression–probably a constraint of their interview question.