System verilog assertion

SystemVerilog
,
4

The 100ps is a hold time, and has no effect on the assertion.
What you have as an assertion is correct. Below is a simple model, with a hold time (though not needed) along with the simulation results. It works as expected.

module risefall; 
	bit clk, a=1'b1; 
	ap_rf: assert property(@(posedge clk) $fell(a) |-> ##2 $rose(a) ); 
	
	initial forever #5 clk=!clk; 
	
	initial begin 
		@(posedge clk);
		repeat(200) begin 	
			@(posedge clk);
			#1;
			if (!randomize(a)) $error();  
		end 
	end
endmodule

775×472 39.9 KB

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us

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  • Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
  • Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
  • Component Design by Example ", 2001 ISBN 0-9705394-0-1
  • VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
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