In reply to sraja:
Are you saying that relative to your TXCLK, reset_signal has a 100ps hold time, and of course TXCLK has a period > 100ps?
From your diagram above, ($fell(reset_signal)at the posedge of tick 2.
Then $rose(reset_signal)) should occur on the posedge of tick 12.
So this ($fell(reset_signal) |-> ##10 $rose(reset_signal)) should have worked.
Am I missing something?
If the 100ps is asynchronous, then it’s a different story.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SystemVerilog Assertions Handbook 3rd Edition, 2013 ISBN 878-0-9705394-3-6
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115