System verilog assertion : timing checks between to signals

SystemVerilog
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3

In reply to ben@SystemVerilog.us:

In reply to sumit089:
Use realtime and either first_match or the goto oprator. Otherwise, it looks okay.
With the ##[1:$] in the consequent, the assertion can never fail.

 
property clk_p (int time_period);
realtime current_time;
($rose(data_en),current_time=$realtime) |=> 
($rose(data_ack)[->1] ##0 (time_period<= $realtime - current_time));
endproperty
property clk_p (int time_period);
realtime current_time;
($rose(data_en),current_time=$realtime) |=>
first_match(##[1:$]($rose(data_ack))) ##0 (time_period<= $realtime - current_time));
endproperty

Ben systemverilog.us

Hi Ben,

I am confused with the use of the assignment operator in the second part of the property?
What’s the motive behind that? Is the time-difference stored in the time_period and then used somewhere else in the testbench to check?
But then the question comes, since this is a concurrent property, does the property actually stores a copy of time_period or the changes to it actually affect the global time_periodd variable?