System verilog assertion : |-> operator with intersect construct

SystemVerilog
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In reply to dave_59:

In reply to kishan patel:
The intersect operator only works between two sequences. You are trying to intersect two properties.

So, for intersect it is not valid …

But it is valid for “and”

   property and_1;
     @(posedge clk) (a |-> ##[1:2] b) and (c |-> ##[2:3] d);
   endproperty

//above code is running without any compilation error.

so, can you tell me what is the exact problem while using it with intersect because, “and” & “intersect” is almost same. only the difference is length of sequence.

or it is like LRM says that we can’t use implication_operator with “intersect” but we can use it with “and”.

Please clear my doubt.
Thanks