Synthesizable SVA | Clock frequency checker without using realtime data type

SystemVerilog
4

I’m not sure why you’re trying to build this check into the design, if you could detail why you want to do that some more that could help.

Whether you choose to use a “reference” clock or have a counter fill and then you divide down, either way, a built-in check that uses a clock on the die will be affected by any process variations and so the results will be approximate. For this built-in assert are you planning on an external clock reference or is the concept to have everything internal to the design?

Given that variation is to be expected, and assuming that less accurate checking is acceptable(is it?), it may be good to allow for the checks to have a form to the effect of:

if(stopwatchCounter == 1000) PASS;
else FAIL;

But you may want some slack:

if(stopwatchCounter inside {900,1100}) PASS;
else FAIL;