Syntax error :token is '['

SystemVerilog
3

In reply to sharino:

Output ‘f’ can’t be driven from an always_ff block like that, since it’s declared as a net. You’ll need


output logic signed [ELEM_OUT_SIZE-1:0] f;

Furthermore, since you are harnessing the power of SystemVerilog you can do away with K&R port declarations, and give types to the parameters:


module MAC #(parameter int ELEM_IN_SIZE = 8, parameter int ELEM_OUT_SIZE = ELEM_IN_SIZE * 2)
(
    input logic clk,
    input logic rst,
    input logic signed [ELEM_IN_SIZE - 1:0] a, b,
    input logic signed [ELEM_OUT_SIZE - 1:0] prev_f,
    output logic signed [ELEM_OUT_SIZE - 1:0] f
);