Synchronizing DUT and reference model

UVM
3

In reply to dave_59:

Thanks for the reply Dave. I am trying to implement an assertion for above situation and not use delays in my scoreboard.

I have the following assertion:


always @(posedge A)
       begin
            A= 1'b0;
            assert_property (signal_check) 
       end

property signal_check;
 @(posedge clk) ##[1:10] B === C;
endproperty

The assertion starts at posedge of A and then checks if C takes B’s value in 1 to 10 clock cycles.
My question is:
What happens to the assertion after it passes. Say C took B’s value in 2 cycles. Does the assertion stop and start again when there is a posedge on A ?