In reply to chr_sue:
Thanks, that is another solution, just to spy a signal inside the DUT and use it in the predictor.
I tend always to verify the DUT as a black box and avoid the extraction of intern states to my predictor. Doing this with a spy/bind signal has the disadvantage of not using TLM handshaking of your monitor and a second disadvantage is that, in case we simulate the NETLIST, the hierarchy or that signal (path and name) could change.
A third thing i see (could be good or bad) is that i want to predict in an static manner, i mean, if there are 3 clock delays needed after the trasnsaction reachs the predictor, then there should be also 3 clock delays in the future. (if some DUT modification will be done). If i use the intern/spy valid signal, then i am having a predictor which adapts to the DUT (with the spy of that signal). That could have negative or positive effects.
But YES that is a good solution.
Thanks!!