Thanks Dave (you are the best),
Do you mean that i have to implement this waiting in the Monitor?, or in the environment? or in the predictor.
Because this depends on each DUT, would not be more convenient to implement it inside the predictor which has the specific implementation for that DUT?
And, do you have a link or an example for this construction?
you mean using the analysis FIFO described here:
https://verificationacademy.com/verification-methodology-reference/uvm/docs_1.1d/html/files/tlm1/uvm_tlm_fifos-svh.html
The description says: " Typical usage is as a buffer between an uvm_analysis_port in an initiator component and TLM1 target component."
Yes, that is what a want. A buffer between those points, but
how do i have control of which value of the buffer do i want to take?
I mean, in the end, i have to wait so many clocks (the specific clock for the interface i will predict) that are needed to align with the triggering output event of the DUT. In order to do that, i need to take the clock period information from the interface, and know how many clocks i need to wait for the DUT depending on its implementation.
Now, that i know that the recommended UVM solution is the buffering (with analysis_port), then i wonder if creating my own shift register FIFO which is read on each DUT clock will be also an accepted solution. The FIFO input will have, as input, the previous monitored value if there is no new value from the Monitor or the new value from monitor. In that FIFO, i know, that each place/value of the FIFO would be to look in the past of the pipeline structure of the DUT. Then i only need which place of the FIFO i need to read in the predictor to be aligned with the DUT.
Is there something like that in UVM?
I do not know if i can do the same with the analysis FIFO. (i hope i could make me understand)
Thanks.