In reply to Yogeshk:
// a signal 'done' is asserted within 100 clock cycles after 'start' is asserted,
// and 'error' is never asserted during this period?
$rose(start) |-> (done[=1] and !error[*1:100]) intersect 1[*100];
Ben Cohen
Ben@systemverilog.us
Link to the list of papers and books that I wrote, many are now donated.