SVA: Using $changed in antecedent

SystemVerilog
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2

In reply to sonofthesand:

use a ##1 as the first delay, basically a shift in when the goal of the assertion starts 
assert property( @(posedge CLK) disable iff (!NRST)
##1 $changed(OUT1) ##0 !SYNC1
|-> ##59 $changed(OUT2) ##0 !SYNC2
$display("sync ok"); else $display("sync NOT ok");

Ben systemverilog.Us