SVA to check if the signal changes on the clock edge

SystemVerilog
2

In reply to Sudarshan:

I am looking for a system verilog assertion to check if the signal changes on the posedge of clock (rising edge of clock and signal are aligned). I tried below assertions but did not seem to work.
assert property (@(posedge clock) (clock & en) |-> $rose(sig_a) )
assert property (@(posedge gsync) (en) |-> sig_a )
but both did not work. Can you please help.

See discussion at https://verificationacademy.com/forums/systemverilog/sv-assertion/checker-stable-input-posedge-clock.
assertions uses events for the checks, and if in1 changes sometime before the @(posedge clk) the assertion will succeed, instead of failing. Actually, assertions are not intended for timing checks. In the audio field, undersampling is called “aliasing” Aliasing - Wikipedia
The best solution is to use the SystemVerilog timing checks that are defined in the language.

1800:31.3 Timing checks using a stability window wrote:

The following timing checks are discussed in this subclause:
$setup $hold $setuphold
$recovery $removal $recrem
These checks accept two signals, the reference event and the data event, and define a time window with
respect to one signal while checking the time of transition of the other signal with respect to the window. In general, they all perform the following steps:
a) Define a time window with respect to the reference signal using the specified limit or limits.
b) Check the time of transition of the data signal with respect to the time window.
c) Report a timing violation if the data signal transitions within the time window.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
For training, consulting, services: contact Home - My cvcblr