SVA Simple challenge: Write design and SVA for a down counter

In reply to Prabhu Kamalanathan:

I would like to see RTL design and assertions for this simple loadable down-dounter with a terminal count. As I said, I already have the design and the assertions, and the testbench, and it work fine. This is a simple challenge, if any of you is willing to share.
Will share my design after a reply fith a design an assertions.


// interface 
module dncounter  #(WIDTH = 4) (
  output logic[WIDTH-1:0] count_out,  // counter ouput
  output logic termcount,  // terminal cont when counter==0
  input logic[WIDTH-1:0] data_in, // initial count, loaded with ld_enb
  input logic ld_enb, count_enb, rst_n, clk // active lo reset
  );

Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us