[SVA] signal rises and stays stable check -> how to write an assertion?

SystemVerilog
21

In reply to ben@SystemVerilog.us:

Edited above code with the cycle_delay_const_range_expression


initial // with the cycle_delay_const_range_expression
    ap_a_init1: assert property(@(posedge clk) $rose(a)[->1] |->
      always[3:$] (b));

Ben SystemVerilog.us