[SVA] signal rises and stays stable check -> how to write an assertion?

SystemVerilog
3

In reply to ben@SystemVerilog.us:

Thank you a lot, Ben!

But how could I disable this assertion?

Let’s consider some TestBench, which has two events - event1 and event2.
When event1 happens, I’d expect the signal “a” should rise and stay stable (high) until event2.
When event2 happens, I’d like to release (disable/disassert) the assertion (after event2, the signal “a”) can receive any value.
Number of cycles between event1 and event2 is unknown.