In reply to ben@SystemVerilog.us:
If you make a mistake you admit it.
a |=> b[=2] ##1 c ; // is eauivalent to
a |=> !b[*0:$] ##1 b ##1 !b[*0:$] ##1 b ##1 !b[*0:$] ##1 c;
// #35 clk=1, a=0, b=1, c=1 // Property Passed or Fail ?
// Because of !b[*0:$] ##1 c;
// equivalent to
!b[*0] ##1 c or !b[*1] ##1 c or...
// also
!b[*0] ##1 c // is equivalent to
C // b can be 1 or 0
// property is true at time 35 because b==1
My apologies