Why SystemVerilog assertions are evaluated in observed region, although the values are sampled in preponed region ?

In reply to Harshit : Why SystemVerilog assertions are evaluated in observed region, although the values are sampled in preponed region ? Keep in mind that SystemVerilog must emulate concurrency using a sequencial non-concurret processing computer. Before getting into an example that explains th…

@Ben Thanks for your inputs. In which region immediate assertions are sampled and evaluated ?

In reply to Harshit : The signals in an immediate assertion are never sampled; they are evaluated at the point in the procedural process they appear. The action block of a simple immediate assertion executes at that point as well. It’s the same an if-statement except you get the coverage recorded w…

In reply to ben@SystemVerilog.us : Hi Ben, Can you explain why “%t sampled q=%d, current q=%d, past q=%d, var w=%d” is getting printed before “%t sampled q=%d, current q=%d, past q=%d, var y=%d” although it has ##0 delay ? In assertion the $display will get evaluated in active region or re-active …

In reply to samirxd : In reply to ben@SystemVerilog.us : Can you explain why “%t sampled q=%d, current q=%d, past q=%d, var w=%d” is getting printed before “%t sampled q=%d, current q=%d, past q=%d, var y=%d” although it has ##0 delay ? NO, but I believe it is how the tool handles the printing. …

In reply to ben@SystemVerilog.us : Thanks Ben.

In reply to samirxd : ##0 is sequence concatenation indicating the beginning of the second sequence is in the same clock tick as the end of the first sequence. Since these are both single clock sequences, they are concurrently true .There is no implied ordering between the sequence match items. Howe…

In reply to ben@SystemVerilog.us : Hi Ben , If I were to define the subroutine as :: function automatic int getq(); return k ; // Simply return ' k ' without defining variables . endfunction : getq I observe the updated value of k is assigned to local variable…

In reply to hisingh : In reply to ben@SystemVerilog.us : function automatic int getq(); return k ; // Simply return ' k ' without defining variables . endfunction : getq I observe the updated value of k is assigned to local variable w . function bit test(); $display("%…

In reply to ben@SystemVerilog.us : Hi Ben , I am a little confused about the clocking event ( @ posedge clk ) in the property A2C . Concurrent assertion is evaluated in Observed region whereas the event i.e @ posedge clk occurs in Active Region . So by Observed region the …

Verification Academy

SVA evaluation

SystemVerilog

samirxd September 8, 2021, 2:54pm 9

In reply to dave_59:

Thanks Dave.