In reply to ben@SystemVerilog.us:
Hi Ben ,
I am a little confused about the clocking event ( @ posedge clk ) in the property A2C .
Concurrent assertion is evaluated in Observed region whereas the event i.e @ posedge clk occurs in Active Region .
So by Observed region the event trigger has passed by then .
So what triggers the property A2C if it’s being evaluated in Observed Region ?
Can I say the clocking event triggers the property , but the expression is checked
later in observed region using the values sampled in pre-poned region