SVA: condition met between two disabled sections not showing pass/finish

SystemVerilog
,
9

In reply to ben@SystemVerilog.us:

In reply to Adarsh Santhosh:
// ON your other question
done[->1] |=> strong( !a[->1] ##1 !a[*0:])); // DO THIS instead done[->1] |=> s_always( !a[->1] ##1 !a[*1:]));





Hi Ben,

Can you share syntax of s_always?
Im getting an expected left bracket [ error at s_always.