In reply to ben@SystemVerilog.us:
Let’s say here signal a is a cycle counter and not related to any signal in the assertion.
Then, it would be ok. Right?
ap_1: assert property(@(a) b[->1] !c s_until (a == 'd1000))
b and c independent of a
In reply to ben@SystemVerilog.us:
Let’s say here signal a is a cycle counter and not related to any signal in the assertion.
Then, it would be ok. Right?
ap_1: assert property(@(a) b[->1] !c s_until (a == 'd1000))
b and c independent of a