SVA: condition met between two disabled sections not showing pass/finish

SystemVerilog
,
11

In reply to ben@SystemVerilog.us:

Hi Ben,

2 questions on above.

  1. whats the difference between #1 and #=# . Does the second option mean 0 or 1? if so, wouldnt ##0 be sufficient. Since, we have only signal “a” of interest.(“a” goes low and “a” stays low)
  2. since, we cant use s_always. How can we get a strong fail? Lets say “a” going low in consequent never happens.