SVA (Ben Paper reference 2018) { hard} within ,firstmatch

SystemVerilog
,
5

In reply to ben@SystemVerilog.us:

OK, The within works, but something is going on with the or


// Works OK 
ap_go_data_vld: assert property( @(posedge clk)
          $rose(go) |-> go && $changed(vld)[->1] // or  go && $changed(data)[->1]
           within
         ($rose(go) ##1 $fell(go) [->1])) pass1=pass1+1; else fail1=fail1+1; // for debug

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