I am reading the book, A practical guide to system verilog assertions by Ramanathan Meyapan. I am confused with the following diagram. This is to check a |-> b;
The book says on clock cycle 1, it will not sample the signal a, as it is not stable by that time.
But if we go by this logic, many assertions will fail , where signal aligns to clock boundary. For example, let us say we want ready to be high for 2 clocks, if it is exactlt 2 clocks high aligning with the clock, it will fail because first clock will miss that signal is high! sample wave shown below:
The waveform states that on clock cycle 1, signal ‘a’ isn’t sampled due to instability where ‘rdy’ isn’t stable by the first clock edge. However, this logic causes issues with assertions, like expecting ‘rdy’ to be high for exactly 2 clock cycles, which fails because the first cycle misses the high signal. The waveform illustrates ‘clk’ and ‘rdy’, highlighting the sampling issue at the clock boundary.
I think the author used a shortcut. Signals a and b are sampled in the preponed region of a time slot, meaning their values are taken from the previous time slot. New values are assigned to signals a and b synchronously with the rising edge of the clk signal, what takes place in the active or NBA regions of the current time slot. The assertion itself, on the other hand, is evaluated in the reactive region, which comes after the active and NBA regions. At tick number 1, the target value of signal a has not yet been established, hence the result of the assertion is marked as ambiguous.
You need to show us the stimulus code in SystemVerilog to explain better what is going on. There is no such thing as as signal exactly aligned with the clock. Sampling looks as the value of a signal before the clock edge.
Hi Dave
This is not a real scenario that I am facing, I am wondering that if such ready signal comes exactly aligned to clock, can it cause issue, because of preponed region ? The confusion has started after it was mentioned in the book that signal will not be captured at first clock edge.(i have pasted snippet above)
