SVA Assertion

SystemVerilog
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3

In reply to dave_59:

In reply to sraja:
Can you write your description in the form:

HI Dave,

  1. if (PC0 == 1) then after some clock cycles (pop == 1)
  2. PC1,PC2,PC3 signals shouldnot goto high in between condition 1.(i.e in between $rose(PC0) and $rose(pop).

Hope this is clear.

-Regards,
-Sravan.