SV soft constraints usage and benefits

SystemVerilog
5

In reply to dave_59:

Hello Dave,

“a. The user doesn’t need to explicitly know the name of the constraint block in order to disable the soft constraint, just the name of the variable”

Tried an example for above statement



class packet;
  rand  bit [3:0] addr;
   
  constraint addr_range { soft addr inside {5,10,15}; }
endclass

 module static_constr;
  initial begin
    packet pkt;
    pkt = new();
     
     
    $display("Before Constraint disable");
    repeat(2) begin //{
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end //}
     
    //disabling constraint
    pkt.addr.constraint_mode(0);
     
    $display("After Constraint disable");
    repeat(2) begin //{
      pkt.randomize();
      $display("\taddr = %0d",pkt.addr);
    end //}
  end
endmodule

Error:-Could not find field/method name (constraint_mode) in ‘addr’ of 'pkt.addr.constraint_mode

->Could you please let me know ,if i miss interpreted the statement ?
Thanks in Advance