SV question on ternary operator

SystemVerilog
1

what is the difference between below 2 statements . consider that “foo” is register variable and can take 0,1,x,z value . Lets say foo=“x” . What will be output c in both the cases ?

//case 1 
c = (foo) ? a: b ;

AND  
//case 2 
if (foo) c =a 
else c =b

?

2

Good example of X-prop (https://documentation-service.arm.com/static/5ed106a8ca06a95ce53f8966?token=) - run few simulations and experiment to learn more on this.

Good luck

3

Thanks @user60 . Got the answer . I saw there are many good scenarios in this mentioned document .
case1 - when foo =x , c will get x propogated .
case 2 - when foo = x , c will get “b” as a output .
Above output we will get in the simulation .when we come to synthesis . both the cases will give you same output . “x” propgation enabled setup in Simulation will give exact silicon behaviour .