[SV LRM 2017] Special provision of unpacked union

SystemVerilog
,
2

In reply to juhi_p:
A union may contain any datatype. SystemVerilog does not define the layout in memory for any type, so unpacked unions are not that useful except for maybe this provision. If you have the following two structs in a union

  typedef struct {
    int A;
    real B;
    bit [31:0] C;
    int D;
  } s1_t;
  typedef struct {
    int A;
    real B;
    bit [15:0] C1;
    bit [15:0] C2;
    int D;
  } s2_t;
  union {
    s1_t s1;
    s2_t s2;
  } U;

The LRM says you can write to U.s1.A and read it back from U.s2.A intact (same for element B). But there is no similar guarantee for any other members. A compiler might choose to align C1 and C2 to 32-bit word boundaries. so there’s no guarantee how s1.C overlaps s2.C1 and s2.C2, or whether s1.D overlaps s2.D. Only packed unions guarantee alignment over bits.