Hi HAH,
Not sure how Mentor would perceive this - but Synopsys’s VCS has already extended SystemVerilog to support all the 3 you have asked in Beta/LCA form since few years. But sure they are not standard yet. We need strong users like yourself to demand this to language committee.
Dave - when you say “this is right forum” - may I know if you channelize such requests to SV-EC like committees? Since SV is a “controlled” IEEE standard, individuals/small companies can’t really contribute - unfortunate, but reality!
Ajeetha, CVC