SV inteface task behaviour called from a class fork

SystemVerilog
1

Have some odd behaviour while using interface task to poll an address in a class fork when first occurence triggers all others, despite their trigger condition wasn’t met.

interface my_ifc(
         input my_clk 
        ,input [31:0] addr
        ,input            write
        ,input [31:0] wdata);

clocking cb_clk @(posedge my_clk);
        default input #1step ;
        input addr;
        input write;
        input wdata;
        endclocking : cb_clk

   task automatic wait_for_write(bit[31:0] a_data , bit[31:0] a_addr);
        $display("%0t start poll addr [%0h] a_data [%0h] actuall %0b data[%0h]addr[%0h]",$time , a_addr,a_data,cb_clk.write,cb_clk.wdata,cb_clk.addr);
       @(posedge cb_clk.write && (cb_clk.wdata == a_data) && (cb_clk.addr == a_addr));
       $display("%0t Accepted  addr [%0h] a_data [%0h] actuall %0b data[%0h]addr[%0h]",$time,a_addr,a_data,cb_clk.write,cb_clk.wdata,cb_clk.addr);
   endtask
   endinterface

In my class I kick off three instances of the task in fork…join_none manner .

task my_task(int a_ind = -1) ;
  automatic bit [31:0] temp_addr = (a_ind == 0)  ? 'h80000 : (a_ind == 1) ? 'h180000 : 'h30000 ;
  while (1) begin
  my_ifc.wait_for_write('h8,temp_addr );
  //do something
  end 
endtask

task run_phase();
  fork
   my_task();
   my_task(0);
   my_task(1);
  join_none 
endtask

What I get is that once addr = 'h30000 is written all the rest polls are triggered too .
And moreover the actual addresses are printed correctly in all cases.
The log print is :

94.0ns Accepted addr [180000] a_data [8] actual 1 data[8]addr[30000]
94.0ns Accepted addr [80000] a_data [8] actual 1 data[8]addr[30000]
94.0ns Accepted addr [30000] a_data [8] actual 1 data[8]addr[30000]