In reply to dave_59:
In reply to sva_user:
Maybe you need to show an example of what the design looks like without the bind. I don’t understand why you want to instantiate the module fifo_assertions inside the top level testbench. I thought you only wanted to instantiate the fifo_assertions inside the module FIFO. Also, once you have started using SystemVerilog, there is no longer a distinction between Verilog and SystemVerilog modules; it’s all one language. The bind construct can target any module regardless of whether it was originally coded for Verilog, and regardless of where in the hierarchy it is.
So if your FIFO is
module FIFO(ports);
reg Full;
reg Empty;
endmodule
and it is instantiated throughout your design
module sub_component(ports);
FIFO u23(ports);
endmodule
module sub_sub_component(ports);
FIFO u34(ports);
endmodule
The using the bind command below will instantiate the fifo_assertions module in every FIFO instance.
bind FIFO fifo_assertions fa_1(Full,Empty);
The bind construct effectively modifies the FIFO module as if you had written it as
module FIFO(ports);
reg Full;
reg Empty;
fifo_assertions fa_1(Full,Empty);
endmodule
Now when ever a FIFO is instantiated, another fifo_assertions module is instantiated underneath it.
Hi Dave,
I have followed what you said about bind assertions in the testbench top level, but how do I switch these assertions off in UVM testcase, because $assertoff doesn’t seem able to switch assertions off anymore?
I use following bind statment before:
bind dut.inst_sub_module.inst_sub_sub_module.inst_FIFO FIFO_assertionin inst_bind(.*);
and switch all assertions off in uvm testcase run phase with “$assertoff(0);”
Thnaks