SV Assertions for Arbiter priority

SystemVerilog
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9

In reply to Vignesh Raghavan:

I guess there is no necessity for a break statement inside the begin…end block.

You’re correct, however, the break gives you the following advantages:

  1. It clarifies the requirements in that once you find the high bit being true, the lower order bits are irrelevant, or don’t care.
  2. Efficiency.
    Ben SystemVerilog.us