Hi, If I have to test a priority encoded arbiter with say, 4-inputs (request signals) and 4-outputs (grant signals), What assertions are required for verifying this arbiter?

The following is a generalized solution for a large vector up to 30 bits (i.e., 29:0]). The concern for 32 bits is that setting v[31]to 1’b1 creates a negative number and would cause error in my req < v. One solution for larger vectors would be to use time data type, which is a 4-state data type, …

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SV Assertions for Arbiter priority

SystemVerilog

Vignesh_Raghavan July 20, 2014, 7:00am 6

In reply to ben@SystemVerilog.us:

Thanks Ben…