In reply to ben@SystemVerilog.us:
Note: the v=0 (below) is not really necessary and can be deleted since v is initialized to 0 anyway.
Making v=0 clarifies the intent.
(req[i]==1’b1, v=0, v[i+1]=1’b1) ##0 req < v |->
Thus, this would be OK too
(req[i]==1’b1, v[i+1]=1’b1) ##0 req < v |->
Ben