SV Assertions clock period

SystemVerilog
,
3

You need to declare the local variable curr_time within the property declaration.
what you have above is illegal

property p_tclk;
  realtime curr_time;
@(posedge SCLK) ('1, curr_time = $time) |-> @(posedge CLK) (tclk == ($time - curr_time));
endproperty

ap_tclk : assert property (p_tclk);

// The following has formal arguments. 
property Tclk (logic SCLK,time tclk);
...

   Ben Cohen
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