SV assertion

In reply to Junior:
If I understand you correctly, you are trying to do something like:


(evt) |=> .signal(signal_1 & signal_2)[idx]==b;  //  signal[idx] === b

//Weird! .signal(signal_1 & signal_2) results is a vector of bits, like 4'b1010
// I don't believe that 4'b1010[idx] is legal 
// At least, I never used it that way
// Try this instead
wire temp[`SIZE:0];
assign temp=(signal_1 & signal_2);
(evt) |=> .signal(temp)[idx]==b;  //  signal[idx] === b