In reply to Yuankun:
The reason I initially used the always @(posedge clk) !ack is because I was not sure without doing some 1800 research of the clock flows through from the sequence to the property, so I took the safe mode.
Many many years ago, when I was learning VHDL, I had lots of syntax/legality questions. Finally, my mentor got fed up with me and said the following:
If you are in doubt about what is legal or illegal, write a test code and simulate it.
I can assure you, the simulator tool knows the LRM much better than you.
:)
Here, I followed that advice instead of digging into 1800, and the answer is YES.
The clock does flow through from the sequence to the followed-by property
$rose(req)|->##[1:10]ack #=# always !ack); // WORKS OK, IS LRGAL