In reply to ben@SystemVerilog.us:
Hi Ben,
thanks for replying.
I didnt know about the strong concept. I will read more on that and try it.
// did you READ MY PREVIUS COMMENT?
// An assertion of the form
// seq |-> expr1 ## [1:$] seq2
// can only fail if expr1 is false. <<<**********
// If expr1==1 then there are an infinite number of possibilities
// for seq2 to be true
Ok. Im a little confused here. I thought only infinite limit($) had that issue and I won’t be having this issue when Im using goto operator. I need to check more about goto operator.
even then, isnt “(c && (reg2[16:0] == 17’hF))” the expr1. So c low means expr1 is 0.
or is the (1,display(“”); the expr1?
You’re throwing the kitchen sink!
An antecedent with a single possible match need not a first_match.
a first_match is needed when there are multiple possible matches, like in
a ##[1:$] b |-> …
I might not have been clear.
There are possibilities for multiple matches where antecedent is true. a and b stays high for multiple clock cycles. maybe i should have used $rose instead.
Or do u mean antecednt can have a sequence with multiple events and then if we need first of those events, use first_match?
In short, I was looking for all of these events to happen in exact sequence( when a and b is high at a clock edge for the first time) and if even one of the steps doesnt happen or changes order, assertion should error out.