SV assertion for clock gating & Reset check

[S.P.Rajkumar.V]

In reply to ben@SystemVerilog.us:

Hi Ben,

Thank you very much for reviewing the assertions and providing valuable inputs.

But I am still facing issue in the following scenario:
Reset enable is de-asserted → held for some time → and then reset en is asserted again.

I have coded the following asertion for this scenario:

property rst_disable_chk;
  @(posedge ref_clk)
    $fell(reset_en) |-> (reset_n throughout reset_en [->1]);
endproperty

As the async reset assertion is immediate, the reset_n signal changes directly with reset_en change, where-as the throughout is expecting the old value of reset_n at the time of reset assertion and hence a assertion failure is issued.

So, how do I handle the through-out check here? Please suggest.

Thanks,
Rajkumar.