In reply to ysaini:
Keep in mind that an assertion is a statement that a given property is required to hold.
SVA is just a notation with a set of rules to write assertions. Long before SVA or PSL, verification engineers wrote assertions in Verilog and VHDL, and before that, the verification was visual with scopes (if you’re my age). The point here is that for this case, consider writing just SystemVerilog code. Your solution sounds plausible.
Ben Cohen
http://www.systemverilog.us/ ben@systemverilog.us
- SVA Handbook 4th Edition, 2016 ISBN 978-1518681448
- A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5
- Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0
- Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 978-1539769712
- Component Design by Example ", 2001 ISBN 0-9705394-0-1
- VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1
- VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115