Support back to back transactions in UVM driver

UVM
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5

In reply to chr_sue:

I tried support it in driver and this is working, but I think it is little dangerous the way I did it :

my_driver.sv:



bit new_req;

virtual taskmain_phase(uvm_phase phase);
   super.main_phase(phase);
 
   forever begin
      seq_item_port.get_next_item(req);
      new_req = 1;
      drive_data(reg);
      new_req = 0;
      seq_item_port.item_done();
   end
endtask : main_phase
 
 
// --------------------------------------
 
virtual protected task drive_data(item curr_item);
 
   // start transaction 
   @(posedge vif.clk);
   vif.valid <= 1;
   vif.data <= curr_item.data;
 
   fork 
      begin
         // release the bus 
         #0; // To be done last in simulation tick 
         if (new_req == 0 ) begin
            @ (posedge vif.clk);
            vif.valid <= 0;
            vif.data <= $random();
         end
       end
   join_none
endtask:drive_data

I added a new signal new_req that used as a flag to indicates if new req assert when the current item still didn’t release the bus.

I’m worried from raise issues on this signal.